#+title: vhdl microcode quarter so far
#+author: screwtape
* I have a theme rather than a plan
Still, it's shaken down in what *could* have been a Project Managed way.
** DONE Read up on VHDL
DEADLINE: <2023-11-08 Wed> SCHEDULED: <2023-11-02 Thu>
tl;dr
|------------------|
| reichenbacher |
| logic_11164 |
| numeric_std |
| simulation |
| entities |
| architectures |
| processes |
| signals |
| d-flipflops |
| FSMs |
| S-RAM |
| Synthesisability |
|------------------|
One thing is that VHDL is reeeally small. The whole thing is basically TYPEs in terms of existingly defined TYPEs (so a BYTE might be a STD_LOGIC_VECTOR of some NATURAL length from STD_LOGIC_11164, and a MEMORY some natural length of said defined BYTEs.
TYPEs also have OPERATIONs defined on them, which are basically the most minimal DEFMETHOD. So NUMERIC_STD can cast STD_LOGIC_VECTORs to its SIGNED/UNSIGNED TYPEs which have the usual integer arithmetic / + - % defined on them.
On the other hand, this small set of rules largely for dealing with SIGNAL assignment have a standardised way of simulating them in terms of DELTA timesteps every time a SIGNAL gets <= assigned that is a sensitivity for another signal (or process).
*** Three problems
**** The systems being designed are very big
Above I mentioned defining a MEMORY in terms of BYTEs which might be used for an S-RAM, yet we are often planning to harness hundreds of kilobytes in an implicitly orchestrated way. The amelioration for this is to constrain the target as much as possible. In our case, we are trying to reach an abstract implementation of a wholly defined microcode language and processing for the second time.
**** VHDL is very resource poor
There's basically integer arithmetic on customisable bytes used in switch/case assignments and you have to build everything out of that in time with rising_edge(CLOCK).
**** What actually synthesises is basically an oral tradition
Reichenbacher emphasises that plenty of good-seeming RTL (synthesisable) code won't synthesise or won't synthesise correctly for lots of target devices simply because the backend implemented for the standard expected clock edges to look like this rather than like that, or that resetable D-FLIPFLOPs would be symbolised in some particular way. In our case, AMS has said a behavioural (ie correct but non-synthesisable) architecture is fine.
** DONE Functional model of VHDL in LISP
DEADLINE: <2023-11-15 Wed> SCHEDULED: <2023-11-09 Thu>
I spent much less time than I would have liked this week organically growing the bones of a subset of RTL-style VHDL in lisp. My goal, which we kinda started getting to was that instead of masquerading as a VHDL engineer, painstakingly tapping out lines of synthesisable VHDL in VIM, which my neighbor does, instead I am imagining VHDL as a domain specific language inside lisp for implementing a network of very strict signal assignments suitable for
- delta-time-steppable VHDL standard simulation of BEHAVIOURAL lisp forms
- Those literal lisp forms and operations (lambdas) #'FORMAT to correct VHDL
- The literal lisp forms and operations (lambdas) play well for ACL2 logic
and implicitly, the lisp should be common lisp compatible with zetalisp (so no CLOS or MOP basically).
*** Implementation so far
My general strategy for extremely incremental image-based construction of closures forms has been like this:
1. VHDL objects have prototype s-expressions that look like a let-over-lambda with
no lambda
2. There's a DEFUN which lexically encloses a #'COPY-TREE of the prototype
and provides a lambda for querying and modifying that s-expression.
3. The s-expressions built using *this* closure
1. Evaluate to behavioural VHDL simulation closure (partially done)
2. Are passed to: (format t *object-type-control-string* s-expression)
to produce human-readable VHDL code.
3. Since there is always basically a MAKE-LOAD-FORM available,
Form-before -> form-after
is suitable for ACL2 applicative logic theorems.
What connects these together is that the argument to everything is the same S-expression and intends to meet the three suitabilities in the last section.
It's not ready for the light of day, but a sometime version of one of my incrementally grown DEFUNs is in an appendix here.
** TODO Write a bunch of VHDL (in the coming fortnight)
DEADLINE: <2023-11-29 Wed> SCHEDULED: <2023-11-16 Thu>
I have a way of creating and growing/modifying/pruning VHDL logic, so for the next two weeks I am going to use it to create a bunch of VHDL
1. Patching up/finishing my notion of VHDL s-expression closures
2. Introducing FORMATing to plain VHDL code
3. Introducing a subset of VHDL standard simulation over those s-expressions
I'll be starting the fortnight writing stereotypical VHDL samples, and try to evolve into fragments of the lispm microcode.
** Latent futures
Heavy duty visualisation is part and parcel with electronics design, but I didn't settle on a method (though GHDL has integrated waveform stuff).
While I think LISt Processing was suitable for incrementally and experimentally producing S-expressions for closures for VHDL s-expression closures, these keywordy closures are really the mechanics that should sit underneath a domain specific language. I'm inclined to base the language on integration of CLIM2 standard COMPLETIONs and PRESENT/ACCEPTation of GESTUREs, but this doesn't play with ZETALISP and McCLIM would want to take over the electronics visualisation, whereas ZETALISP wants me to use MACSYMA for visualisation and whatever LOGO is for interactive design.
* Appendix: SIGNALs at one point this week
#+begin_src lisp
(defvar *signal-form*)
(setq *signal-form*
'(let ((name nil)
(sensitivities ())
(type-constraints ())
(update-case ((t))))
(values)))
(defun new-signal (&optional (old-form nil)
&aux
(form (or old-form (copy-tree *signal-form*))))
(symbol-macrolet
((name-location (cadr (first (cadr form))))
(sens-location (cadr (second (cadr form))))
(constrain-loc (cadr (third (cadr form))))
(case-location (cadr (fourth (cadr form)))))
(lambda (&key set-name get-name get-form
add-sens del-sens senses
add-case get-case cases set-case
constrain constraints del-constraint)
(cond
(set-name (setf name-location set-name))
(get-name (values name-location))
(get-form (values form))
(add-sens (push add-sens sens-location))
(del-sens (setf sens-location
(delete del-sens sens-location)))
(senses (copy-list sens-location))
(add-case
(if (member add-case '(t others))
(setf (cdar (last case-location))
(cdr add-case))
(push add-case case-location)))
(get-case (copy-tree (assoc get-case case-location)))
(cases (copy-tree case-location))
(set-case (setf (cdr (assoc (car set-case) case-location))
(cadr set-case)))
(constrain (push constrain constrain-loc))
(constraints (copy-tree constrain-loc))
(del-constraint (setf constrain-loc
(delete del-constraint
constrain-loc
:test 'equal)))
(t (values *signal-form*))))))
#+end_src