|
| PicassoCTs wrote:
| Its also used on simple GPUs? As In, lots of math functions
| stamped down to low level operations ala RISC?
|
| https://alchitry.com/projects/gpu
| http://ijsetr.com/uploads/435216IJSETR3253-390.pdf
| contingencies wrote:
| If you dig this, see also this recent post
| https://news.ycombinator.com/item?id=33326360
| willis936 wrote:
| It's used in the Propeller 2.
|
| https://www.parallax.com/propeller-2/
| mysterydip wrote:
| I was about to say, this was my first introduction to CORDIC.
| Works for my purposes just fine. Fun platform to program on.
| smcin wrote:
| My MSEE thesis [0] innovated on classical CORDIC to modify it to
| reuse the three 18-bit adder/subtractors (one each for
| X-,Y-,Z-stages) into one Booth-recoded multipler retiring 6
| bits/cycle. Hence it could complete an 18 x 18b multiplication in
| only three cycles (as opposed to 18 cycles or worse (+overheads)
| for classical CORDIC). Pretty neat, for almost zero extra
| gatecount (only a few muxes and control logic).
|
| (The motivation was that CORDIC with Walther's 1971 improvements
| performs great for trigonometric/hyperbolic/arc-functions,
| Euclidean distance, sqrt and also allows (bit-serial) division
| and multiplication - but still slow compared to array
| multipliers. This stuff was used in 1970s multifunction
| calculators (when area.)
|
| Since I decided to not do a PhD or do followup publications, my
| work proved the concept worked, then pretty much vanished into
| the conf literature.
|
| The concept is straightforward; if anyone out there wants to
| synthesize it on a Xilinx or similar, or do a soft-macro
| (Verilog/VHDL), and get some performance numbers, drop me a line.
|
| Also, Timmerman, Hahn, Hosticka did some good innovation in the
| 1990s on scaling, pipelining and latency. [1] But for most use-
| cases, you don't pipeline unless you really need to trade higher
| throughput off against minimal gatecount/silicon area and
| latency.
|
| And in the 1990s, there was interest in CORDIC for matrix
| triangularization and SVD.
|
| [0]: "Hybrid multiplier/CORDIC unit", IEEE ICASSP-99
| https://ieeexplore.ieee.org/abstract/document/758297
|
| [1]:
| https://scholar.google.com/scholar?hl=en&as_sdt=0%2C5&q=cord...
| contingencies wrote:
| I've got some low end but semi recent FPGA devkit hardware that
| I'm unlikely to use. Our company is about to switch continents
| so I am liquidating assets. If you'd like the hardware, it's
| yours. I sent you an email using the address in your paper.
| peter_d_sherman wrote:
| >"CORDIC and closely related methods known as pseudo-
| multiplication and pseudo-division or factor combining are
| commonly used when no hardware multiplier [or floating point] is
| available (e.g. in simple microcontrollers and FPGAs), as _the
| only operations it requires are additions, subtractions, bitshift
| and lookup tables._
|
| >"CORDIC uses simple shift-add operations for several computing
| tasks such as the calculation of trigonometric, hyperbolic and
| logarithmic functions, real and complex multiplications,
| division, _square-root calculation_ , solution of linear systems,
| eigenvalue estimation, singular value decomposition, QR
| factorization and many others."
| [deleted]
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